1. Field of the Invention
Example embodiments of the present invention relate to slave devices, which may support dynamic clock gating, and methods of operating the same.
2. Description of the Related Art
Related art portable mobile devices (e.g., mobile phones, personal digital assistants (PDA), laptops, notebook computers, etc.) may draw power from one or more batteries. In such a related art mobile device, power may be preserved by reducing power consumption of components, for example, memories, input and output devices, etc.
Power consumed by a related art mobile device may be divided into, for example, an active power and a stand-by power, and reducing the stand-by power may be more effective and/or easier than reducing the active power. For example, a related art method of reducing an operation clock frequency of component device or a related art method of reducing an operating voltage of the component device may be used to reduce the active power of a related art mobile device.
A related art method known as, for example, dynamic clock gating may be used to disable clocks applied to logic blocks of a related art mobile device when the logic blocks are not enabled such that power consumption due to these clocks may be reduced.
FIG. 1 is a block diagram illustrating a related art clock gating circuit coupled to a target circuit, which may be a target of a dynamic clock gating method.
Referring to FIG. 1, a target circuit 100 may represent a circuit, which may be a target of the related art dynamic clock gating method. For example, the circuit may include operating clocks, which may be dynamically gated in order to reduce power consumption. Clock gating circuit 150 may represent a circuit that performs the dynamic clock gating.
The clock gating circuit 150 may include a d-latch 160 and an AND gate 170. The target circuit 100 may transmit a status signal STATUS to an input node D of the d-latch 160, and an external clock CLK, which may be generated by an external clock source, may be applied to a clock node G of the d-latch 160 and the AND gate 170.
In response to the status signal STATUS, a determination may be made as to whether a gated clock GATED_CLK may be transmitted from the AND gate 170 to the target circuit 100. For example, when the status signal STATUS transmitted to the D-latch 160 has a low logic level (e.g., logic ‘L’ or ‘0’, and the target circuit 100 is on the process of receiving or transmitting data), the AND gate 170 may be activated and the gated clock GATED_CLK may be provided from the clock gating circuit 150 to the target circuit 100. Alternatively, when the status signal STATUS has a high logic level (e.g., logic ‘H’ or ‘1’ the target circuit 100 is not on the process of receiving or transmitting data), the AND gate 170 may be deactivated and the gated clock GATED_CLK may be gated, for example, the gated clock GATED_CLK may not be provided to the target circuit 100.
In another example, the related art devices, to which the above power reduction technique may be applied may be coupled, and exchange information, through the bus. The bus may be a communication channel, which may be coupled to various devices, for example, a wire including an address line, a data line and a control line. In addition, the bus may represent a protocol for signal transmission between one or more master device and one or more slave devices.
The master devices may be devices, which may control all, or substantially all, bus operations. The master device may be, for example, a CPU (Central Processing Unit), and several master devices may exist in a bus system. The slave devices may operate in response to commands transmitted from the master devices. The slave devices may interpret commands from the master devices and operate in response to the commands from the master devices.
FIG. 2 is a block diagram of a related art bus system, which may include master devices and slave devices.
Referring to FIG. 2, a related art bus system 200 may include a bus BUS, master devices M01, M02, . . . , and slave devices S01, S02, S03, . . . , which may be coupled to the bus BUS. A related art bus system may also include various components such as bus arbiters and decoders, which are not shown in FIG. 2.
Related art methods may be used for improving performance of the bus system. For example, a related art pipe-lining method may allow bus transactions to begin before previous bus transactions have concluded. The related art pipe-lining method may allow time delays between read (or write) requests and actual read (or write) transactions to be used by the other transactions. A related art pipe-lined bus system may be a bus system, which uses the related art pipe-lining method to improve an overall performance of the bus system. For example, a bus transaction may be divided into several phases including an address phase and a data phase. A related art pipe-lined bus system may start an address phase initiated by a slave device during a data phase of another slave device.
FIG. 3 is a timing diagram illustrating a related art parallel bus operation of several slave devices using a related art pipe-lined bus architecture.
Referring to FIG. 3, an address phase A1 may be an address phase of a first slave device, and an address phase A2 may be an address phase of a second slave device. A data phase D1 may be a data phase of the first slave device and may be based on address information included in the address phase A1. A data phase D2 may be a data phase of the second slave device and may be based on address information included in the address phase A2.
As shown in FIG. 3, the address phase A2 of the second slave device and the data phase D1 of the first slave device may be processed, for example, simultaneously. By using a related art pipe-lined bus architecture, the bus system may increase the throughput of the bus system.
If dynamic clock gating is introduced to the related art pipe-lined bus system, a bus transaction of a slave device may be overlapped by bus transactions of other slave devices. Each slave device may monitor a bus master in order to determine whether an address phase of the new bus transaction designates the respective slave device. However, when an operating clock applied to a slave device is cut off (e.g., interrupted) using dynamic clock gating, the slave device may lose the address phase initiated to the slave device, and each slave device in a related art pipe-lined bus architecture may remain in the active state to detect another address phase. This may result in excessive current consumption in related art pipe-lined bus architectures.